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rev.4.00 jun. 29, 2004 page 1 of 10 HD74LVC1G97 configurable multiple?function gate rej03d0015?0400z rev.4.00 jun. 29, 2004 description the HD74LVC1G97 has configurable multiple ?function gate in a 6-pin package. the output state is determined by eight patterns of 3?bit input. the user can choose the logic functions and, nand, or, nor, inverter, non? invert buffer, data selector. low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. features ? the basic gate function is lined up as renesas uni logic series. ? supply voltage range: 1.65 to 5.5 v operating temperature range: ?40 to +85c ? all inputs v ih (max.) = 5.5 v (@v cc = 0 v to 5.5 v) all outputs v o (max.) = 5.5 v (@v cc = 0 v) ? output current: 4 ma (@v cc = 1.65 v) 8 ma (@v cc = 2.3 v) 24 ma (@v cc = 3.0 v) 32 ma (@v cc = 4.5 v) ? all the logical input has hysteresis voltage for the slow transition. ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD74LVC1G97cpe tbs-6v cp HD74LVC1G97cle wcsp-6 pin tbs-6av cl e (3,000 pcs/reel) article indication k 2 y m marking year code month code
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 2 of 10 function table inputs output in2 in1 in0 y llll llhl lhlh lhhh hl l l hl hh hhl l hhhh h : high level l : low level pin arrangement (bottom view) (top view) y 16 34 in0 height 0.5 mm 0.5 mm pitch 0.17 mm 6?ball (cp) 0.23 mm 6?ball (cl) 0.9 mm 1.4 mm gnd v cc in1 in2 5 2 pin#1 index logic diagram in0 in1 in2 y
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 3 of 10 function selection table logic function figure no. 2 to 1 data selector 1 2?inputs and 2 2?inputs or with one input inverted 3 2?inputs nand with one input inverted 3 2?inputs and with one input inverted 4 2?inputs nor with one input inverted 4 2?inputs or 5 inverter 6 non?inverter buffer 7
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 4 of 10 logic configurations figure 1. 2 to 1 data selecter a b 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a /b v cc y y a a /b b figure 2. 2?inputs and gate b 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y y a b y a b figure 4. 2?inputs and gate with a input inverted y b a b 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y y a b y a 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y figure 6. inverter y a 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y figure 7. non?invert butter figure 3. 2?inputs or gate with a input inverted b 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y y y a b a b b y a b y a b 1 (in1) (in2) 6 2 (gnd) (v cc ) 5 3 (in0) (y) 4 a v cc y figure 5. 2?inputs or gate
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 5 of 10 absolute maximum ratings item symbol ratings unit test conditions supply voltage range v cc ?0.5 to 6.5 v input voltage range *1 v i ?0.5 to 6.5 v ?0.5 to v cc + 0.5 output : h or l output voltage range *1, 2 v o ?0.5 to 6.5 v v cc : off input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to v cc continuous current through v cc or gnd i cc or i gnd 100 ma 143 cp package thermal impedance ja 123 c/w cl storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. the input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 5.5 v maximum. recommended operating conditions item symbol min max unit conditions supply voltage range v cc 1.65 5.5 v input voltage range v i 05.5v output voltage range v o 0v cc v ?4 v cc = 1.65 v ?8 v cc = 2.3 v ?16 ?24 v cc = 3.0 v i ol ?32 v cc = 4.5 v ??4 v cc = 1.65 v ??8 v cc = 2.3 v ? ?16 ? ?24 v cc = 3.0 v output current i oh ? ?32 ma v cc = 4.5 v 020 v cc = 1.65 to 1.95 v, 2.3 to 2.7 v 010 v cc = 3.0 to 3.6 v input transition rise or fall rate ? t / ? v 05 ns / v v cc = 4.5 to 5.5 v operating free-air temperature t a ?40 85 c note: unused or floating inputs must be held high or low.
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 6 of 10 electrical characteristics ta = ?40 to 85c item symbol v cc (v) min typ max unit test condition 1.8 0.8 ? 1.4 2.5 1.2 ? 1.7 3.3 1.6 ? 2.3 v t + 5.0 2.3 ? 3.0 1.8 0.4 ? 0.7 2.5 0.6 ? 1.0 3.3 0.9 ? 1.4 v t ? 5.0 1.5 ? 2.0 1.8 0.4 ? 0.7 2.5 0.4 ? 0.8 3.3 0.4 ? 0.9 threshold voltage ? v t 5.0 0.4 ? 1.0 v 1.65 to 5.5 v cc ?0.1 ? ? i oh = 100 a 1.65 1.2 ? ? i oh = ?4 ma 2.3 1.9 ? ? i oh = ?8 ma 2.4 ? ? i oh = ?16 ma 3.0 2.3 ? ? i oh = ?24 ma v oh 4.5 3.8 ? ? i oh = ?32 ma 1.65 to 5.5 ? ? 0.1 i ol = 100 a 1.65 ? ? 0.45 i ol = 4 ma 2.3 ? ? 0.3 i ol = 8 ma ??0.4 i ol = 16 ma 3.0 0.55 i ol = 24 ma output voltage v ol 4.5 ? ? 0.55 v i ol = 32 ma input current i in 0 to 5.5 ? ? 5 av in = 5.5 v or gnd i cc 5.5 ? ? 10 v in = v cc or gnd, i o = 0 quiescent supply current ? i cc 3 to 5.5 ? ? 500 a one input at v cc ?0.6 v, other input at v cc or gnd output leakage current i off 0??10 av in or v o = 0 to 5.5 v input capacitance c in 3.3 ? 3.5 ? pf v in = v cc or gnd note: for conditions shown as min or max, use the appr opriate values under recommended operating conditions.
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 7 of 10 switching characteristics v cc = 1.80.15 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time t plh t phl 3.2 14.4 ns c l = 30 pf, r l = 1.0 k ? in y v cc = 2.50.2 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time t plh t phl 2.0 8.3 ns c l = 30 pf, r l = 500 ? in y v cc = 3.30.3 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time t plh t phl 1.5 6.3 ns c l = 50 pf, r l = 500 ? in y v cc = 5.00.5 v ta = ?40 to 85c item symbol min max unit test conditions from (input) to (output) propagation delay time t plh t phl 1.1 5.1 ns c l = 50 pf, r l = 500 ? in y operating characteristics ta = 25c item symbol v cc (v) min typ max unit test conditions 1.8 ? 22 ? 2.5 ? 23 ? 3.3 ? 23 ? power dissipation capacitance c pd 5.0 ? 26 ? pf f = 10 mhz test circuit l note: c includes probe and jig capacitance. c l measurement point r l * from output
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 8 of 10 input in phase output 90% 10% t plh t phl v i gnd v oh v ol t phl t plh 90% v ref v ref v ref v ref v ref v ref 10% ? waveforms out of phase output v oh v ol notes: 1. input waveform : prr 10 mhz, zo = 50 ? . 2. the output are measured one at a time with one transition per measurement. t r t f 1.80.15 2.50.2 3.30.3 5.00.5 v i c l r l v cc v cc / 2 v cc / 2 v cc / 2 vref v cc (v) 2 ns 2 ns 2.5 ns 2.5 ns v cc v cc 3 v 30 pf 1.0 k ? 500 ? 500 ? 500 ? 30 pf 50 pf 50 pf 1.5 v inputs t r / t f
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 9 of 10 package dimensions tbs-6v eiaj package code jedec code mass (g) lead material 0.001 ?? ? symbol dimension in millimeters min typ max a 0.50 0.15 0.35 0.05 0.05 0.20 0.19 0.90 1.40 0.50 0.20 0.20 0.15 0.17 0.10 a 1 a 2 b d e e x y 1 y zd ze e e d zd ze e a1 a2 a c b a 12 pin #1 index area c c b seating plane 6 b c x m a b c x m y 1 // c y c
HD74LVC1G97 rev.4.00 jun. 29, 2004 page 10 of 10 tbs-6av eiaj package code jedec code mass (g) lead material 0.001 ?? ? symbol dimension in millimeters min nom max a 0.50 0.185 (0.315)* 0.05 0.05 0.20 0.25 0.90 1.40 0.50 0.20 0.20 0.20 0.155 a 1 a 2 b d e e x y 1 y zd ze e e d zd ze e a1 a2 a c b a 12 pin #1 index area c c b seating plane 6 b c x m a b c x m y 1 // c y c *reference value.
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